Meet Ayman

Name: Ayman Z. Rizk
Research interest: Ultra-low power microprocessors
Email: arizk@masdar.ac.ae

Research Summary

KT/q limit

The trend for modern consumer computing is low power super handheld devices like the recently released iPads and super smart phones like the iPhone. These devices will require ultra-low power microprocessors. Figure 1 shows projected sub-threshold leakage power increase when you follow Moore’s Law by doubling logic on a chip every generation. Clearly, the leakage power will be of the order of several 100’s of watts beyond 90nm. Solving this leakage issue with novel devices will be of utmost importance for chipmakers for future generations.

Sub-threshold leakage or off-state leakage has become a roadblock to device scaling due to increased power consumption for nano-scale devices. The lower limit to this leakage is governed by the fundamental thermodynamic KT/q limit, which is 60mV/dec at room temperature.

The KT/q limit applies to all devices whose current is determined by transport over a barrier that is controlled by the input voltage.  However it does not apply to devices based on a carrier injection method such as impact ionization (IMOS) and tunneling (Tunneling FETs). The problem is that IMOS and TFETs require very large electric fields counter to the low power application trend.  Recently Berkeley showed a feedback device that requires a pre-charge step making it difficult to implement in production.

As part of my masters thesis I will be studying the proposed device as shown in Figure 3 (a) and (b). The structure has four gates that contact an ultra-thin Si body sandwiched between a n-type source and p-type drain.  By modifying the gate work-functions and the voltage applied potential barriers can be created to make N+/P/N/P+ thyristor like structure without doping. The thyristor like structure can be biased to create a positive feedback mechanism and a large current can flow.   Figure 2 shows a sample Id vs. Vd characteristic with sub KT/q switching.

DRAM scaling

DRAM memory technology is reaching a fundamental roadblock.  Traditional 1T/1C devices are becoming costly to scale due to the limitations in lithography.  These low power handheld devices will require enough memory for streaming video and other modern day applications.  In traditional 1T/1C DRAM, the capacitor scaling has reached a brick wall due to lithography limitations.   As a result, a low power 1T solution to the DRAM will be of vital importance to the DRAM industry at large. For DRAM, a plethora of research into novel replacements has been demonstrated.  Most notably are TRAM (Thyristor) and Z-RAM (Impact Ionization) that both require very large operating voltages. This positive feedback device can be optimized by modifying the metal work-function and the Vg applied to reduce the operating voltage. Also the work-function can be optimized to create potential barriers needed for very long retention times. Hence, it can be used as a promising memory device.

High Speed Nanoscale Flash Memories

The demand for high-density, low-cost, low-power/voltage, and high speed (programming, erase and read operations) semiconductor memory will lead to current nonvolatile flash memories to proliferate into new approaches such as nanoparticle floating gate and single/few electron memories. This allows the tunnel oxide to be scaled down more aggressively because weakspots now erase only the nanoparticles above it. If conventional channel hot electron (CHE) programming is used for nanoparticle arrays, it leads to non-uniform programming only near the drain end. Subsequently, Fowler-Nordheim (FN) erasure into the source will not erase these nanoparticles. Generally, programming and erasure has been demonstrated in individual cells using uniform FN tunneling between the channel and nanoparticle array floating gate.  However, this may be impractical in flash memory cell arrays from an architecture and speed point of view.

Ayman’s work

Fig. 1 Subthreshold Leakage (Watts) vs Technology (from Intel)	Fig. 2  Id-Vd of feedback device with sub KT/q switching characteristics.
Fig. 3 (left) Feedback device structure, (right) with proper biasing and gate workfuntion a Thysistor type structure can be created without doping